1. Field
This disclosure relates generally to a non-volatile memory, and more specifically, to a non-volatile memory with reduced charge fluence.
2. Related Art
Thin film storage non-volatile memory arrays suffer from charge trap-up problem. In particular, repeated write/erase cycles result in electrons getting trapped in the dielectric layers of the thin film storage cells. This is because each time a memory cell is erased and programmed, electrons are tunneled to and from a floating gate of the memory cell. Some of the electrons while being tunneled get trapped in the dielectric layers of the floating gate. Trapped electrons reduce the write/erase endurance of the non-volatile memory. The number of electrons that get trapped is a function of the threshold voltage window, i.e., the difference between the threshold voltage of the memory cell in the programmed state and the threshold voltage of the memory cell in the erased state. Conventional non-volatile memories have a large threshold voltage window resulting in a larger number of electrons getting trapped in the dielectric layers of the thin film storage cells corresponding to these non-volatile memories. As explained above, this reduces the write/erase endurance of such non-volatile memories.
Accordingly, there is a need for a non-volatile memory with reduced charge fluence.